展期论坛 | 国际先进封装设备技术与工艺论坛，议程及嘉宾阵容抢先看

本演讲导入AI时代泛半导体概念，分享华为韬定律， 重点介绍AI核心互联技术，包括硅通孔，塑封料通孔， 玻璃通孔，埋入式硅桥互联和光电共封， 同时分享了AI时代刚需的芯片异构集成和高频高速新材料技术和相关的智能化jc2技术。

This talk introduces pan-semiconductors in the AI era and Huawei's Tao Law. It highlights key AI interconnection technologies: TSV, TMV, TGV, EMIB and CPO. It also discusses mandatory technologies for the AI era: heterogeneous integration, high-frequency high-speed materials and intelligent inspection.

演讲聚焦异构集成与芯粒先进封装解决方案。内容涵盖先进封装面临的多物理场强耦合、跨尺度建模、热管理及可靠性挑战，系统级电-热-力-流多物理场仿真能力矩阵，以及AI+EDA协同优化与STCO设计-仿真-工艺闭环体系。重点介绍XDFOI高密度异构集成与SiP系统级模组两大技术平台，探讨垂直堆叠架构、晶圆级系统（SoW）在高性能计算与AI大模型领域的应用前景，展现从设计到量产的全链条技术实力与生态协同理念。

AI 算力驱动产业深度变革，先进制程持续微缩，Chiplet、3D 堆叠等先进封装工艺快速迭代，芯片集成度与算力密度陡增，对测试系统的算力带宽、测量精度与全链路管控能力提出颠覆性挑战。国内高端封测产能加速扩张，但核心测试设备与全流程量产方案长期依赖外部供给，自主可控不足成为产业发展核心瓶颈。我司推出自研 SOC ATE 测试机以及系列产品，依托 AI HPC 架构构建全栈测试平台，具备全套方案与全生产流程交付能力，为先进封装产业提供自主可控的核心支撑。

Driven by AI computing power, advanced process scaling and rapid iteration of Chiplet and 3D stacking technologies have sharply lifted chip integration and computing density, posing disruptive challenges to test systems’ bandwidth, accuracy and full-link management. China’s fast-expanding high-end packaging sector faces a core bottleneck: long-term reliance on imported test equipment and full-cycle solutions limits independent controllability. We present self-developed SOC ATE testers and related products. Our AI HPC-powered full-stack test platform delivers complete solutions and full production workflow capabilities, underpinning self-reliant development of advanced packaging.

随着AI、高性能计算（HPC）和HBM等应用迅速发展，先进封装已成为延续摩尔定律和实现异构集成的重要驱动力。然而，Hybrid Bonding、TSV、先进互连及超薄晶圆加工等新技术的导入，也对制造工艺和量产良率提出了前所未有的挑战。

本次演讲将聚焦先进封装制造中的关键技术难题，包括高深宽比结构加工、铜填充与平坦化、混合键合界面控制、晶圆翘曲与边缘管理以及超薄晶圆加工等内容，并分享Lam Research如何通过领先的刻蚀、沉积、电镀、清洗与工艺控制技术，解决行业挑战，帮助客户实现更高良率、更高可靠性和更低制造成本。

Driven by the rapid growth of Artificial Intelligence (AI), High Performance Computing (HPC), and High Bandwidth Memory (HBM), advanced packaging has become a key enabler for extending Moore's Law and advancing heterogeneous integration. However, the adoption of emerging technologies such as Hybrid Bonding, Through-Silicon Vias (TSVs), advanced interconnects, and ultra-thin wafer processing has introduced unprecedented challenges in manufacturing processes and production yield.

This presentation will focus on the key technical challenges in advanced packaging manufacturing, including high aspect ratio structure fabrication, copper fill and planarization, hybrid bonding interface control, wafer warpage and edge management, and ultra-thin wafer processing. The session will also highlight how Lam Research leverages its industry-leading etch, deposition, electroplating, cleaning, and process control technologies to address these challenges, helping customers achieve higher yield, improved reliability, and lower manufacturing costs.

在AI、HPC与Chiplet等技术驱动下，先进封装已成为性能突破的核心。然而，HBM堆叠、异质集成等应用在追求超薄与高密度互联的同时，也带来了晶圆易翘曲、多材料加工损伤、系统良率难以保障等严峻挑战。其根源在于，传统孤立的单点工艺已无法满足系统级制造对精度、可靠性与效率的协同要求。

元夫半导体认为，破局之道在于工艺链的深度融合与协同创新。我们推出的SDBG工艺解决方案、High clean修边减薄抛光一体机、激光开槽解决方案、激光钻孔方案等，并非设备的简单串联，而是从工艺提升的角度将减薄、抛光、激光切割等环节深度耦合。通过协同设计实现芯片超薄化（如厚度<100μm）的同时，将切割崩边与损伤降至最低，直接提升了芯片的机械可靠性与电学性能。

我们致力于成为客户的协同创新伙伴，提供先进封装工艺整合解决方案，帮助客户系统性地攻克从制造难点到量产高良率的挑战，共同夯实先进封装的基石，驱动产业未来。

为了应对芯片制造中的技术挑战、成本问题和不断增长IO需求，先进封装技术成为首选。先进封装技术面临的挑战是：实现生产过程中零缺陷的同时并提高生产效率，赋能产品快速导入市场。X射线无损检测技术是解决挑战的必要方法之一。

传统X射线系统采用二维检测技术，无法分离芯片内部各层信息，导致无法检测到芯片内部缺陷，因此，无法应用于先进封装芯片的检测。

Comet Yxlon全新推出的CA20系列，在三维计算机断层扫描（CT）技术基础上研发出全自动检测和全自动缺陷识别解决方案。在高速完成检测的同时，确保检测结果具备可靠性、可重复性、可追溯性。

CA20系列的功能同时具有可扩展性和可升级性，确保您的投资并为您将来的潜在检测需求做好准备。

Advanced packaging technology is the preferred choice to address the technical challenges, cost issues, and growing IO needs in microchip manufacturing. The challenge for advanced packaging technology is to achieve zero defects in the manufacturing process while improving productivity and empowering products to be rapidly introduced to the market. x-ray non-destructive testing technology is one of the necessary solutions to these challenges.

Traditional X-ray systems utilize 2D inspection technology, which is unable to separate the information of each layer inside the chip, resulting in the inability to detect defects inside the chip, and therefore cannot be applied to the inspection of advanced packaging chips.

Comet Yxlon's newly launched CA20 series has developed a fully automated inspection and fully automated defect recognition solution based on 3D computed tomography (CT) technology. The CA20 series is a fully automated inspection and defect identification solution based on 3D CT technology, which ensures reliability, repeatability, and traceability of the inspection results while completing the inspection at high speed.

芯片的功耗和TIM 简单历史，从50多年处理器芯片的历史看，功耗从intel 4004的2瓦发展到现在英伟达R200的2000瓦，芯片功耗是芯片设计，晶圆，封装需要解决的最头疼也是最核心问题：需要Co-design。下面3方面深度讨论：

1. 过去铟作为TIM 的发现过程和它的应用及优缺点;

2. 当前垂直取向石墨烯 TIM 是 AI & HPC最佳TIM1，TIM1.5，和TIM2的解决方案，在性能，稳定性，可靠性都优于别的材料；

3. 未来TIM 的发展方向及相关材料，比如金刚石等。

Over the IC 50 years history, power consumption has increased from 2 watts in the Intel 4004 to 2000 watts in the NVIDIA R200. Chip power consumption is the most troublesome and core issue that chip design, wafer fabrication, and packaging need to address, and co-design is required. The following three aspects will be discussed in depth:

1. The past discovery process of indium as a TIM, its applications, and its advantages and disadvantages;

2. Currently, vertically oriented graphene TIM is the best TIM1, TIM1.5, and TIM2 solutions for AI & HPC, its outperforming other materials in performance, stability, and reliability;

3. The future development direction of TIM and related materials, such as diamond.

后摩尔时代，先进封装已然成为突破芯片性能瓶颈、赋能算力升级与架构革新的核心核心赛道。本报告深耕先进封装技术创新与落地应用，整合2.5D/3D堆叠、晶圆级封装、硅中介层堆叠、混合键合等主流核心工艺，依托重布线层RDL、硅通孔TSV、超薄晶圆加工、翘曲精准控制等关键技术，实现算力芯片、存储、传感器件异构融合与纳米级高密度互连。通过重构产业制造流程，整合晶圆制造后端工序，优化分层集成模式，大幅提升集成密度、缩减产品尺寸、强化整体运行效能。立足中原区域产业优势，对标行业前沿技术成果，统筹推进先进封装国产化协同研发与产业化落地，在现有工艺基础上打造高可靠、低成本集成解决方案，推动产业降本提质、资源互通、全域联动，加速完善本土半导体产业生态，全面提升我国集成电路产业整体实力与市场竞争优势。

In the post-Moore era, advanced packaging has become a core pathway to break through chip performance bottlenecks, empower computing power upgrading and architectural innovation. This report delves into technological innovation and practical application of advanced packaging, integrating mainstream core processes including 2.5D/3D stacking, wafer-level packaging, silicon interposer stacking and hybrid bonding. Relying on key technologies such as redistribution layer (RDL), through-silicon via (TSV), ultra-thin wafer processing and precise warpage control, it enables heterogeneous integration and nanoscale high-density interconnection of computing chips, memory devices and sensors. By reconstructing industrial manufacturing workflows, integrating backend wafer fabrication procedures and optimizing layered integration modes, it greatly improves integration density, reduces product form factor and enhances overall operational performance. Leveraging the industrial strengths of the Central Plains region, benchmarking cutting-edge global technological achievements, we will coordinate the localized collaborative R&D and industrialization of advanced packaging. Building upon existing processes, we will develop highly-reliable and low-cost integration solutions, drive cost reduction, quality improvement, resource sharing and full-domain collaboration within the industry, accelerate the improvement of the domestic semiconductor industrial ecosystem, and comprehensively enhance the overall strength and market competitiveness of China’s integrated circuit industry.

本次演讲会以先进封装市场趋势为切入点，介绍深硅刻蚀技术在先进封装中的主要应用, 工艺挑战以及中微的创新解决方案。

This presentation will focus on the market trends of wafer-level advanced packaging, introducing the key applications of deep silicon etching technology in advanced packaging, along with process challenges and the innovative solutions provided by AMEC.

在算力需求牵引之下，先进封装已经成为半导体产业增长核心引擎，市场规模持续扩张，同时对工艺、检测成套装备提出更高综合要求。本报告梳理当前先进封装主要技术路线演进方向，分析全球及国内封测产线建设浪潮带来的装备市场机会与现实挑战。

报告介绍华封科技集团的发展定位、全球客户基础、业务规模与跨区域研发制造布局；系统展示公司现有先进封装成套设备体系，包含面向 2.5D/3D、Fan-out 板级封装的贴装键合工艺设备，以及新发布的AOI检测装备，阐述设备如何匹配不同阶段客户的产线建设、良率管控需求。最后从产业协同角度，探讨工艺装备与检测装备协同发展路径，分享全球化装备企业服务亚太先进封装产业建设的实践视角，为行业产线规划与供应链选型提供参考。

Driven by computing-power demands, advanced packaging has become a core growth engine for the semiconductor industry with continuously expanding market scale, meanwhile imposing higher comprehensive requirements on complete-set process and inspection equipment. This report sorts out the evolution of mainstream technical routes for advanced packaging, and analyzes equipment-market opportunities and practical challenges brought by the construction boom of packaging production lines worldwide and in China.

在半导体行业迈向 “后摩尔时代” 的当下，先进封装已成为延续摩尔定律、提升芯片性能的关键路径。随着晶体管尺寸微缩逼近物理极限，先进制程成本飙升，先进封装凭借其提升芯片互联密度、加快通信速度等优势，重要性日益凸显。本报告将展示先进封装及混合键合技术的重要性和北方华创在先进封装上的全套解决方案。

As the semiconductor industry enters the "post-Moore era," advanced packaging has emerged as a key pathway for sustaining Moore's Law and enhancing chip performance. With transistor scaling approaching its physical limits and the cost of advanced nodes soaring, advanced packaging is becoming increasingly critical—offering higher interconnect density and faster interconnect speeds. This presentation outlines the strategic importance of advanced packaging and hybrid bonding, and introduces NAURA's comprehensive portfolio of advanced packaging solutions.

1.TGV工艺良率控制面临的挑战

2.光学量检测在TGV领域的应用

3.TGV全工艺栈点在线量检测解决方案

1. Challenges in Yield Control for TGV Process

2. Applications and Challenges of Optical Measurement and Inspection Technology in the TGV Field

3. TGV Full-Process In-line Metrology & Inspection Solution

本次演讲以《AI浪潮：攻克硅光晶圆级测试的量产难题》为主题，从硅光晶圆测试行业痛点切入，分享联讯仪器面向AI算力时代打造的硅光晶圆量产测试解决方案。

This presentation, themed 《Overcoming High-Volume Testing Challenges in SiPh Wafers》, starts with industry pain points in silicon photonics wafer testing and introduces Semight’s mass-production test solutions tailored for the AI computing era.