PCIM研讨会 | 墙报交流：深耕功率器件封装与可靠性技术，解锁车载驱动、高压变频、高密度功率集成前沿创新

Power Devices, Packaging and Reliability

功率器件、封装技术与可靠性

8月26日 ，13:30-15:00

康勇 | 华中科技大学

本论坛聚焦碳化硅器件封装、功率模块热管理、车载 IPM 可靠性等前沿方向，是宽禁带功率电子领域前沿成果的汇总。内容亮点涵盖 250℃高温陶瓷封装工艺、双面冷却车用 SiC 模组研发、无损键合线故障检测等关键技术研究。参会者可收获器件仿真优化、封装量产、热失效管控等实操思路，十分适合功率半导体封装研发工程师与科研人员参考学习。

景巍 | 赛米控丹佛斯

采用最新的RC-IGBT和SiC器件，智能功率模块（IPM）持续往高效率，小型化的方向发展。本环节将向您展示最新的IPM设计理念，包括热设计，短路能力，和功率循环可靠性。 功率器件载流能力持续提升对功率端子连接的可靠性也提出了更高的要求。本环节向您展最新的Pin针焊接和端子焊接技术，以及高温运行下的封装技术。 精细化建模和仿真将有效指导功率模块的设计和应用。本环节将向您展示极端工况下SiC 器件的结温计算方法，器件热特性及散热系统建模。 芯片嵌入式PCB封装技术正成为行业热点，本环节也将带来最新的可靠性分析进展。 本环节适合从事功率半导体封装设计和应用的工程师和科研人员关注。    

演讲简介：

Modern GDICs incorporate slew-rate control to suppress voltage peaks by shaping transition edges. This paper explains the operating principle and how peak reduction is achieved. It also highlights key design considerations: Vth and hold time vary with temperature, so dynamic delay tuning is required for robust suppression.

New Automotive Grade 1200 V SiC MOSFET-based Intelligent

Power Module for Auxiliary Motor Drive Applications on BEVs

演讲简介：

This paper presents Infineon's new automotive grade 1200V SiC MOSFET-based CIPOS™ Maxi IPM, designed for auxiliary motor drive applications on BEV. The IPM integrates AEC-Q compliant devices such as SiC MOSFET, gate driver, and an NTC thermistor in DCB substrate based package. The IPM offers high power density in a compact form factor. This paper provides a comprehensive overview of the module's architecture, SiC MOSFET technology, electrical characteristics, packaging, and thermal performance.

演讲简介：

Automotive auxiliary motor drives operate under prolonged operation cycles and severe ambient conditions, leading to excessive junction temperature (TJ) of intelligent power module (IPM). Elevated TJ increases power losses and may trigger thermal runaway, resulting in critical reliability and safety issues. Therefore, strict thermal management of power devices is essential. However, in actual system environments, direct TJ measurement via thermocouples or infrared cameras is impractical. Instead, TJ must be tracked using the embedded NTC and heatsink temperature. This paper presents the thermal correlation among TJ, NTC, and heatsink using the new automotive grade 1200 V CIPOSTM Maxi IPM under realistic conditions.

演讲简介：

This research presents a Double Sided Cooled (DSC) power module using Silicon Carbide (SiC) devices, achieving high power density and low thermal resistance. The presented thermal characterization method allows for optimizing ceramics usage and module layout, enabling improved performance, power density and costs. This study contributes to the development of efficient and cost-effective power electronic modules for electric vehicles. This enables the DSC power modules to achieve a much higher power density compared to Single Sided Cooled (SSC) solutions, giving the module class a unique position in the automotive market.    

基于不同的器件建模与优化对SiC MOSFET在极端工况下Tj计算的影响与分析

演讲简介：

本文研究了不同器件的建模与优化方法（SPICE、3D有限元热仿真、PLECS等），对极端工况（如主动短路（ASC）和浪涌电流事件）下SiC MOSFET虚拟结温（Tvj）计算的影响。 首先，介绍了英飞凌的增强型SiC MOSFET SPICE紧凑模型（电热耦合）的结构与特性，及其在特定ASC工况下的Tvj计算与研究。为了继续优化Tvj计算，基于PLECS环境，提出了对器件模型的深度改进：如，在电模型里，利用已校正的器件进行TCAD仿真，获得更可靠的超高温和超大电流的I&V数据；在热模型里，导入温度相关的瞬态热阻抗Zth(T)，同时电路中实现在仿真过程中Zth(T)的在线计算等。基于上述改进的PLECS模型，在不同时间尺度的浪涌电流工况的仿真中，都获得了的不错的Tvj计算优化的效果。最后，在同样ASC工况下，将PLECS仿真，与之前的SPICE和参考的3D有限元热仿真进行了对比研究。在文章最后，结合全文，进行了总结。    

Development of a New Package Supporting Both Through Hole and Surface Mount Types for Fan Applications    

演讲简介：

Developed a new SOPIPM/DIPIPM module with approximately 10% smaller package than SOPIPM while retaining identical pin layout and pitch, thereby preserving creepage/clearance and PCB routing ease. Heatsink‑free thermal tests show only about a 5% temperature increase at low currents. Both through‑hole and surface‑mount terminals are available, providing optimized New SOP (2A) and New DIP (3A) variants for compact fanless applications.    

一种用于双轴伺服系统的紧凑型DIPIPM

演讲简介：

本研究介绍了一种用于伺服系统的先进600V DIPIPM。伺服系统要求更高的载波频率、更大的电机锁定容量和更高的可靠性。为实现这些因素，DIPIPM是一个不错的选择，并已被全球伺服制造商所接受。本文介绍了紧凑型DIPIPM，并进行了比较。本文还分析了在多个DIPIPM共用直流母线应用中地线电路的设计思路，通过优化接地电路来降低电路噪声。现场验证数据证实了这些模块能够在1.5/2kW工作条件下持续运行，使其成为下一代工业自动化解决方案的关键组件。

Efficiency and Thermal Performance Comparison of SiC‑MOSFET and Si‑IGBT IPMs in the SPM31

演讲简介：

Silicon carbide (SiC) based intelligent power modules (IPMs) offer substantial advantages over silicon insulated‑gate bipolar transistor (Si‑IGBT) based IPMs. This paper compares the two device technologies implemented in the same SPM31 package provided by onsemi. Loss and efficiency are evaluated under various operating conditions using simulations based on switching characteristics. In addition, a motor‑drive test bench is employed to verify the thermal advantage of the SiC solution by directly measuring junction temperature under matched operating conditions. The results show that SiC‑based IPMs achieve lower loss and higher efficiency, enabling more compact and thermally efficient designs and positioning SiC-based IPMs as a compelling alternative to Si‑IGBT IPMs in redesigned systems.    

Junction Temperature Evolution of IGBTs under Power Cycling conditions

演讲简介：

This paper presents a thermal simulation study to evaluate the temperature change of a transistor (IGBT) junction under power cycling conditions in an ambient temperature range from -20°C to 55°C. three-dimensional transient thermal model was developed based on a steady-state initial solution with full turn-on heating applied to the power semiconductor devices. Power cycling was implemented using a repeated turn-on and turn-off profile with durations of 180 s and 120 s, respectively, while ramp-up and ramp-down transitions of 900 s were applied to the ambient temperature to represent realistic operating conditions and avoid abrupt thermal shocks.    

实际电机驱动应用中 的IPM 短路失效机理研究    

演讲简介：

智能功率模块（IPM）的短路鲁棒性是变频压缩机等实际电机驱动应用中极其关键的可靠性指标。然而，带载短路工况往往会引发复杂的系统级失效，这是传统基于单管的理想短路测试难以全面覆盖的。通过严密的数学建模、SPICE 仿真以及在商用空调电控板上的硬件实验，本文深入研究了实际三相桥式拓扑下的系统级短路失效机理。首先，研究表明，实际的相间故障会根据瞬态运行状态触发双管短路场景，此时有效跨导的非对称性诱发了非线性电压重分配现象。这迫使特定的绝缘栅双极型晶体管（IGBT）承受绝大部分的直流母线电压Vbus。同时，器件退饱和期间极高的 dv/dt触发了动态米勒效应，导致栅极电压Vge严重抬升，使得局部瞬态电流突破安全工作区（SOA）。此外，本文突出了实际故障回路中非理想寄生电感Lsc的关键作用；在 IGBT 关断瞬间，巨大的感性储能被强制换流至续流二极管中，成为诱发二极管二次局部热失效的首要原因。上述理论机理均通过 IPM 开封后的微观失效形貌分析得到了强有力的物理印证。基于这些发现，本文提出了优化的栅极驱动阻抗设计，成功将峰值短路电流抑制了约 50%，全面提升了系统的整体短路鲁棒性。    

Non-Destructive Bond Wire Failure Detection in SiC Power Transistors Using Reflectometry Signals

演讲简介：

This paper presents a non-destructive estimation of bond wire states in discrete SiC power transistors using EOTPR. We investigate the impact of pin selection, cross-pin aggregation, and window-specific feature extraction, comparing CNN-based, feature-based, and hybrid models. The proposed approach achieves a mean accuracy of 88% for source bond wire state estimation on an unseen device with previously unobserved failure combinations.

Advanced Thermal Management Solutions for Enhanced Compact 3D Power SiP Technologies

演讲简介：

The miniaturization of Power Management Integrated Circuits (PMICs) packaging is increasingly critical due to the rise of smartphones, wearables, and IoT devices. As Moore's Law approaches its physical limits, the adoption of advanced packaging technologies is essential for achieving higher power density, enhanced performance, and a smaller footprint. This shift towards miniaturized PMIC packaging not only meets the demand for compact form factors but also ensures efficient power delivery and robust system integration, positioning advanced packaging as a pivotal enabler for future electronics.

This study introduces an innovative three-dimensional system-in-package (3D-SiP) technology for power IC packaging, exemplified through a low-power PMIC featuring a buck converter, a boost converter, and four low-dropout (LDO) regulators. The proposed architecture utilizes two substrates interconnected via a vertical interconnect scheme, allowing for compact stacking and improved integration. The 3D-SiP structure redefines vertical connectivity by employing surface-mount multilayer ceramic capacitors (MLCCs) as dual-function components alongside copper pillars, thus eliminating traditional interconnect methods like solder balls or metal studs. This architecture achieves a 20% reduction in the X-Y planar area while offering excellent electrical performance, with a package height increase of only 0.27 mm compared to conventional 2D designs. By vertically stacking components, power density is increased, facilitating the integration of future compact power systems, making it ideal for next-generation applications.

In addition to electrical performance, managing thermal behavior is critical for the 3D-SiP architecture, given the heightened power density and limited heat dissipation capabilities. To address these challenges, the study implements optimized thermal management solutions, including enhanced heat spreading layers, improved thermal vias, and strategic placements of copper pillars and metal blocks. Comprehensive thermal simulations reveal a reduction in junction-to-board thermal resistance (ΨJB) from 31.62 °C/W in the baseline design to 23.35 °C/W in the enhanced configuration, alleviating thermal constraints and boosting device reliability. The thermal analysis was carried out alongside a JEDEC 2S2P test board, illustrating the benefits and trade-offs of vertical integration in power ICs, while providing guidelines for future compact power system designs.

Measurements of DC resistance and thermal resistance have been conducted on the baseline 3D-SiP, with future assessments planned for the proposed design. For instance, the Vout-boost path exhibited simulated and measured DC resistance values of 10.27 mΩ and 11.41 mΩ, respectively, reflecting a 10% error margin. Efficiency measurements showed that the performance of buck and boost converters in the 3D-SiP deviated by less than ±1% from a reference circuit. Additionally, the output voltage deviation of the LDO remained within 11 mV, demonstrating that this packaging approach effectively sustains PMIC performance while reducing size.

Thermal resistance measurements focused on ΨJB as a key metric, conducted in compliance with the JESD-51 standard using Simcenter T3STER equipment. The baseline 3D-SiP showed measured ΨJB values closely aligning with simulated results, validating the reliability of the thermal modeling. This study's findings provide significant insights into reducing DC and thermal resistance issues associated with vertical integration of power ICs, offering valuable guidance for developing high-power-density and compact power systems in the future.

雷射焊接於功率模組之應用

演讲简介：

隨著電動車(xEV)與資料中心高效能運算(HPC)技術的蓬勃發展，高功率模組對封裝互連的耐電流能力提出了前所未有的嚴苛要求。然而，在極端高電流環境下，傳統的銲料接合技術往往容易因熱應力與電遷移效應而出現瓶頸，難以提供長期穩定的互連品質，成為限制高功率封裝效能提升的最大痛點。為突破此一技術極限，本次演講將為您深入剖析一項具備革命性潛力的「無銲料雷射銲接互連技術」。本研究透過精密的雷射銲接製程，成功實現了極低阻抗的固態接合。實驗數據顯示，在高電流測試條件下，該技術將接觸電阻大幅降低了約50%；而在機械強度方面，其剪切強度表現更是優異，分別達到傳統銲料的2.3倍與超音波銲接的1.6倍。更重要的是，此創新互連結構已順利通過1000次熱循環測試(TCT)的嚴格可靠度驗證，可做為次世代功率半導體封裝的方案

方波电压下功率模块等离子体清洗最优参数组合研究

演讲简介：

研究了在重复方波电压下，等离子体清洗参数对功率模块中活性金属钎焊基板局部放电行为的影响。采用正交实验设计，系统评估了四个关键参数的影响：气体比例、功率、处理时间和压强。通过极差分析和方差分析确定最佳参数组合。统计分析表明，气体比例是等离子体清洗中唯一具有统计意义的因素。这些发现为优化等离子体清洗方案提供了定量指导，从而提高了电源模块的绝缘可靠性。

适用于250°C中高压碳化硅功率电子器件的陶瓷封装技术

演讲简介：

本文提出了一种经过验证的陶瓷封装解决方案，适用于设计工作温度为250°C的碳化硅（SiC）功率器件。通过电-热-机械耦合仿真，选定氮化硅（Si₃N₄）作为最佳封装材料，因其与SiC具有优异的热膨胀系数匹配度及卓越的机械强度。开发了一种低寄生参数的封装布局，采用纳米银烧结技术进行芯片粘接，测得的功率环路电感为28 nH，与商用分立器件相当。所制备的SiC MOSFET原型已在高温条件下通过实验验证，在250°C的环境温度下表现出稳定的开关性能，且未发生失效。本研究为高温SiC封装提供了系统化的路径，使SiC器件能够在新一代高密度电力电子系统中得到充分利用。

Reliability and Manufacturing Comparison of Flexible and Straight Pin Interconnects for Pin-Array Power Modules

演讲简介：

Pin-array power modules for photovoltaic and energy-storage use pin interconnects between ceramic substrates and PCBs under severe thermal cycling. This study compares soldered “flexible” pins and straight ultrasonic-welded (USW) pins. Flexible pins are elastic up to ±10 µm but fail near 150 N; straight pins offer higher pull strength. Both survived 1,000 thermal shock cycles without degradation, with USW pins offering superior process control.    

高压直流换流阀自循环相变冷却系统压降模型研究

演讲简介：

精确的压降模型对于两相流冷却系统的设计与运行稳定性至关重要。当前主流的两相流摩擦压降模型多针对特定工况条件提出，难以直接适用于高压直流换流阀热管理系统的实际运行场景。基于此，本文结合高压直流换流阀自循环相变冷却系统的特性搭建了专用实验平台，对压降模型进行修正，开展实验并进一步验证修正模型。实验结果表明，修正后的压降模型计算结果与实验数据最大相对误差不超过12%。本文吻合良好的实验结果为自循环相变冷却系统在高压直流换流阀冷却系统中的应用提供了理论支撑与工程参考。

湿度对下一代芯片内嵌式PCB封装可靠性的影响

演讲简介：

芯片内嵌式PCB封装技术因其缩短的信号传输路径、更高的功率密度及更优的散热路径，成为下一代电子系统的有力竞争者。因应用微孔技术显著缩短了互连长度，减小了PCB封装的尺寸。然而，这这种设计中更高的电场强度协同水汽凝结/吸附，增加了爬电失效风险。PCB表面积的减小还要求表面组装组件微型化，并因此增加了电化学迁移的风险。在凝露、偏压载荷与离子污染的协同作用下，阳极发生水解和金属溶解。生成的金属离子在数秒内迁移至阴极并还原为金属枝晶，导致短路故障。这些金属枝晶结构极其脆弱，在维修和更换过程中极易脱落。此外，短路引发的火灾也可能破坏电化学迁移枝晶形成的证据。失效证据的缺失给故障后的根本原因分析带来了挑战。本文系统阐述了因湿度诱发的PCB封装技术失效机理，为下一代芯片内嵌式PCB封装的设计提供了理论支撑与实践指导。

新型六合一SiC功率模块电热可靠性协同分析

演讲简介：

为了满足高功率密度逆变器的需求，本文对NEXIC开发的1200V六合一SiC功率模块进行了全面的电热可靠性协同设计研究。采用综合实验和仿真方法。静态和动态特性，包括输出特性、传输特性、开关能量损耗和短路耐受能力，都是通过实验进行表征的。使用电磁仿真工具提取模块内的杂散电感和互电容等关键寄生参数，从而能够对高频开关行为进行精确建模。基于模块结构的层组成和材料特性构建详细的热阻网络模型，随后通过有限元热模拟和瞬态热测量进行校准。

通过电热耦合分析，确定了模块在指定冷却条件下的连续电流能力和安全工作温度。迭代地解决电损耗和温升之间的相互作用，以确保符合热限制。利用测量和模拟数据，在代表性的功率循环条件下开发和评估了寿命预测模型，考虑了引线键合剥离和焊料层分层等疲劳机制。由此产生的最大输出电流-频率-热阻曲线为工程设计提供了直接指导，实现了不同操作场景下功率密度和热约束之间的平衡权衡。寿命预测结果进一步证实了该模块适用于高可靠性应用，包括牵引传动和航空航天动力系统。

这种涵盖电、热和可靠性领域的多物理场方法为高密度、高可靠性电源模块的设计提供了宝贵的参考。实验结果证实，NEXIC模块具有出色的动态均流和热管理性能，满足苛刻的市场应用的严格要求。

一种基于转模塑封工艺的低感高功率密度功率模块研制

演讲简介：

本文提出了一种转模塑封的Pin针直出式三相全桥功率半导体模块，其中，三相电路集中在同一块衬板上，大大减小了模块的体积，提升了模块的功率密度。同时，辅助Pin针直接从模块顶部直出，有效的的减小了辅助回路的寄生参数，提升了模块的动态抗干扰能力。模块使用转模塑封工艺，抛弃传统的侧框方案，使得模块的直流端子长度得到大幅度的缩减，从而实现较低的寄生电感；考虑到键合线在服役过程中，会有线性疲劳损伤，创新性的使用CuClip技术应用于Si基模块中，消除了键合线在服役过程中带来的失效问题，提升模块寿命

Overview of High Heat Capacitor Materials for eMobility Applications

演讲简介：

Polymer film capacitors are key components in DC-Link modules. Demand for range, fast charging, and efficiency necessitated operation around 150°C. Polymer film material affects capacitor performance at elevated temperatures. An overview of film materials is presented and comparison of films dielectric properties is made.  Breakdown strength (BDS), Permittivity (Dk), Dissipation (Df) and self-healing of the film, and voltage derating of the capacitor at elevated temperatures are discussed.

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