展期论坛 | EDA/IP 与 IC 设计论坛，议程及嘉宾阵容抢先看

随着先进工艺复杂度提升、Chiplet与3D集成快速发展，以及大模型与智能体进入芯片设计流程，传统以人工编排、单点工具和二维设计对象为核心的EDA模式正在发生系统性重构。本文提出“Agent原生EDA与3D-IC原生EDA”双原生技术范式：Agent原生EDA通过结构化工具接口、微工具与微操作、统一设计状态、过程数据归因、事务回滚和确定性签核，使智能体能够完成任务规划、多工具协同、候选探索、结果复测和闭环优化；3D-IC原生EDA则将Die、HBT/TSV、跨层互连、异构PDK、RC、时序、供电、热及DRC/LVS等作为统一三维数据模型中的一等对象，实现划分、布局、时钟、供电、布线与多物理场分析的联合优化。基于这一理念，我们推出 iEDA-3D：一个开源、白盒、可插桩、可验证、可学习和持续进化的智能3D设计基础设施，让Agent真正进入芯片设计内环。

As advanced technologies become more complex, Chiplet and 3D integration continue to grow, and AI agents enter chip design, traditional EDA flows are being reshaped. We propose a dual-native paradigm: Agent-Native EDA and 3D-IC-Native EDA. Agent-Native EDA enables agents to plan tasks, call tools, explore solutions, verify results, and optimize designs in a closed loop. 3D-IC-Native EDA models tiers, dies, HBTs/TSVs, inter-tier connections, PDKs, timing, power, thermal effects, and DRC/LVS in a unified 3D framework, enabling joint optimization across partitioning, placement, clocking, power delivery, routing, and multiphysics analysis. Based on this idea, we introduce iEDA-3D, an open-source and intelligent 3D design infrastructure that brings agents into the chip design loop.

刘军, 现任芯华章科技研发副总裁，AI+EDA部门负责人，硬件逻辑综合部门负责人。目前在芯华章主持AI EDA的研发工作，致力于使用AI技术重塑数字芯片设计和验证流程，毕业于上海交通大学，获电子科学与技术硕士学位，江苏省集成电路学会会员。曾就职于Synopsys美国山景城研发总部，任芯片验证事业部高级研发工程师，回国后主要研究方向为AI EDA、硬件逻辑综合技术，硬件形式化验证以及芯片静态验证技术。带领团队从0到1实现了芯华章形式验证产品GalaxFV/GalaxEC/GalaxEC HEC。长期从事AI EDA，逻辑综合，高性能形式化求解引擎，随机约束求解引擎相关研究工作，获多项国家发明专利。

集成电路产业普遍面临研发到量产周期长、工程验证难以快速落地，测试良率爬坡慢、量产成本高的核心痛点。如何低成本地快速实现工程化量产，提高测试质量和故障覆盖率、快速让产品上市，延长产品生命周期，是芯片公司关注的核心挑战。广电计量聚焦芯片从工程开发到规模化量产的全流程落地，打通晶圆测试、成品FT测试、可靠性验证全链条关键环节，助力新产品快速工程化量产一站式解决。

The integrated circuit (IC) industry generally faces core pain points: long R&D-to-mass-production cycles, slow deployment of engineering verification, sluggish test yield ramp-up and high mass production costs. For chip enterprises, the key challenge is how to realize rapid engineering mass production at low cost, enhance test quality and fault coverage, shorten time-to-market and extend product lifecycles. GRGT focuses on end-to-end chip implementation from engineering development to high-volume manufacturing. By integrating key links throughout the whole chain including wafer testing, Final Test (FT) and reliability verification, it provides comprehensive one-stop solutions to accelerate new products’ engineering mass production.

AI智能化与EDA设计的深度融合，提升企业硬件设计过程中的效率和质量，加速企业生产力的解放和提升。

（1）RISC-V+AI智通融合服务器CPU介绍

（2）大模型适配

（3）应用场景

面向5G/6G、卫星通信、智能汽车等广泛应用，射频系统向高频、高速、高集成演进，芯片、封装与系统之间的耦合日益增强，传统分层设计模式正面临效率与性能协同优化的挑战。下一代射频设计亟需从“芯片设计”走向“芯片—封装—系统”协同仿真与优化。本次分享将聚焦射频EDA技术创新，构建覆盖器件建模建库、射频电路、芯片、模组及系统的协同设计能力，并引入AI多智能体，推动仿真、优化与设计空间探索智能化，加速射频硬件系统的升级迭代。

To meet the demands of broad applications such as 5G/6G, satellite communications, and smart vehicles, radio frequency (RF) systems are evolving toward higher frequencies, faster speeds, and greater integration. As the coupling among chips, packages, and systems deepens, traditional design paradigms face critical challenges in co-optimizing efficiency and performance. Next-generation RF design urgently needs to shift from isolated "chip design" toward "chip-package-system"co-simulation and co-optimization.

This talk focuses on RF EDA technology innovations that build end-to-end co-design capabilities spanning device modeling, library generation, RF circuits, chips, modules, and systems. By incorporating multiple AI agents，it drives intelligent simulation, optimization, and design space exploration, ultimately accelerating the upgrade and iteration of RF hardware systems.