展期论坛 | Chiplet、先进封装与AI算力芯片产业化论坛，议程及嘉宾阵容抢先看

随着Chiplet、2.5D/3D集成、异质集成及背面供电等技术快速发展，先进封装内部的功率密度、互连复杂度和材料界面数量显著增加，热热点、电流拥挤、电迁移、热应力及器件老化等可靠性问题呈现多尺度、多物理场耦合和跨阶段演化特征。传统以设计后验证和失效后分析为主的可靠性评估方法，难以贯通封装设计、制造测试、运行监测与维护决策全过程。面向上述挑战，本报告围绕先进封装全生命周期可靠性管理，介绍从物理机理建模、智能仿真、可靠性设计到在线感知与寿命预测的一体化技术体系。

The rapid development of Chiplet-based integration, 2.5D/3D packaging, heterogeneous integration, and backside power delivery has substantially increased power density, interconnect complexity, and the number of heterogeneous material interfaces in advanced packages. Consequently, reliability concerns such as localized hotspots, current crowding, electromigration, thermomechanical stress, and device aging increasingly exhibit multiscale, multiphysics, and time-dependent characteristics. Conventional reliability approaches, which primarily rely on post-design verification and post-failure analysis, are no longer sufficient to support coordinated decision-making throughout package design, manufacturing, testing, operation, and maintenance. This presentation introduces an integrated reliability design framework for the full-lifecycle management of advanced packaging, covering physics-based modeling, intelligent simulation, design optimization, in-situ sensing, health assessment, and lifetime prediction.

后摩尔时代的半导体产业问题，集中于供应链安全问题上。在晶圆厂微缩能力趋近极限，产能捉襟见肘的背景下，先进封装如何整合材料，设备，服务供应商，通力合作解决需求端问题，是未来产业发展的关键。

The challenges facing the semiconductor industry in the post-Moore era are primarily centered around supply chain security. As fabs approach the physical limits of chip scaling and struggle with constrained manufacturing capacity, the key to future industrial development lies in how advanced packaging can integrate materials, equipment, and service providers to collaboratively address demand-side challenges.

AI算力持续演进，正在推动芯片系统向更高带宽、更高集成度和更复杂的异构异质集成发展。面向3D IC，不同功能、不同工艺节点乃至不同技术体系的Chiplet通过高密度互连与立体堆叠形成复杂系统，设计对象也由单一芯片进一步延伸至跨Die、跨层级的系统协同。随之而来的，不只是互连密度、功耗与热等问题的叠加，更是架构、物理设计、多物理场仿真、工艺等环节之间日益复杂的耦合关系。面对庞大的设计空间和多目标约束，依赖单点工具与串行迭代的传统设计方式正面临新的挑战。

本次演讲，硅芯科技总经理赵毅博士将围绕“AI+3D IC EDA”新设计范式，探讨如何以AI驱动异构异质堆叠下的系统级协同设计。通过构建面向3D IC的创新型工具链，贯通架构设计、物理实现、多物理场仿真、验证及测试等全流程关键环节。并通过硅芯科技3D IC EDA AI Agent——Chips Z及3Sheng EDA工具平台的协同实践，进一步融合先进封装Know-how与AI能力，实现跨层级数据协同、设计空间探索以及多目标自动迭代寻优，推动端到端STCO闭环持续收敛。以AI重塑3D IC设计方法、工具体系与协同流程，推动先进封装从单环节创新走向系统级创新，进一步打开3D IC产业新的“芯层级”。

The continued evolution of AI computing is driving chip systems toward higher bandwidth, greater integration density, and increasingly sophisticated heterogeneous integration. In 3D IC systems, chiplets based on different functions, process nodes, and even technology platforms are integrated through high-density interconnects and vertical stacking, extending the design scope from individual dies to cross-die, cross-layer system-level co-design. This evolution introduces not only increasing challenges in interconnect density, power consumption, and thermal management, but also increasingly complex coupling across system architecture, physical implementation, multi-physics simulation, and process technology. Faced with an enormous design space and multiple competing objectives, conventional design methodologies based on point tools and sequential iterations are encountering growing limitations.

In this presentation, Dr. Zhao Yi, General Manager of Zhuhai Silicon Chip Technology Ltd. (SiChip), will explore a new “AI + 3D IC EDA” design paradigm and discuss how AI can enable system-level collaborative design for heterogeneous 3D integration. By building an innovative toolchain for 3D IC design, key stages across the entire workflow—including architecture design, physical implementation, multi-physics simulation, verification, and testing—can be seamlessly connected.

The presentation will further introduce the collaborative deployment of SiChip’s 3D IC EDA AI Agent, Chips Z, together with the 3Sheng EDA platform. By integrating advanced packaging know-how with AI capabilities, the solution enables cross-layer data collaboration, design space exploration, and automated multi-objective iterative optimization, continuously driving the convergence of an end-to-end closed-loop System-Technology Co-Optimization (STCO) workflow. Through AI-driven transformation of 3D IC design methodologies, toolchains, and collaborative workflows, advanced packaging can evolve from isolated point innovations toward system-level innovation, opening up new possibilities and a higher level of innovation for the 3D IC industry.

LPU的商业化发展机遇；3D混合键合技术打破存储墙；迈特芯3D-TPU芯片技术及优势；迈特芯LPU芯片的应用场景。

Commercialization opportunities for LPU; 3D hybrid bonding technology breaking the memory wall; Metachip 3D-TPU chip technology and advantages; application scenarios for Metachip LPU chips.

传统依赖经验与试错驱动的半导体装备研发模式面临效率与性能瓶颈，本演讲将介绍人工智能在中微公司如何赋能半导体装备的结构设计、控制设计、工艺开发、与运行维护。

Traditional semiconductor equipment R&D relies heavily on engineering experience and iterative trial and error, leading to bottlenecks in development efficiency and performance improvement. This talk will present how AI empowers R&D at AMEC covering structural design, control system design, process development, operations and maintenance.

三叠纪（广东）科技有限公司是成都迈科科技有限公司的全资子公司，立足后摩尔时代三维集成微系统关键材料与集成技术，在行业内率先提出TGV3.0，首次突破亚10微米通孔和填充技术，被四川省国防工办鉴定为整体国际先进，其中通孔尺寸、孔密度和深径比国际领先，是国内玻璃通孔技术的倡导者与引领者。

2022年公司在东莞松山湖建成TGV基板与三维集成封装中试线，并参与组建“集成电路与半导体特色工艺战略科学家团队”，成为国内具有显著特色和优势的TGV研发与生产基地。目前已形成TGV三维封装载板、玻璃基光通信组件、玻璃基IPD无源集成器件、3D微结构玻璃四类产品体系，主要应用在高算力芯片、光通信、三维集成封装、高Q微波/THz器件、光学/射频MEMS、微流控芯片等领域。

3D CHIPS (GUANGDONG) TECHNOLOGY CO., LTD grounded in key materials and integration technologies for 3D integrated microsystems in the post-Moore era, the company was the first in the industry to propose TGV3.0 and achieved a breakthrough in sub-10-micron via hole and filling technology. This accomplishment was evaluated by the Sichuan Provincial Defense Industry Office as internationally advanced overall, with via hole dimensions, hole density, and aspect ratio ranking among the world's leading levels. The company is recognized as a pioneer and leader in glass via hole technology in China.

In 2022, the company completed the construction of a TGV substrate and 3D integrated packaging pilot line in Songshan Lake, Dongguan, and participated in the establishment of the "Strategic Scientist Team for Integrated Circuits and Semiconductor Specialty Processes," becoming a nationally distinctive and advantageous R&D and manufacturing base for TGV. To date, the company has formed four product lines: TGV 3D packaging interposers, glass-based optical communication components, glass-based IPD passive integrated devices, and 3D microstructured glass. These products are primarily applied in high-performance computing chips, optical communications, 3D integrated packaging, high-Q microwave/THz devices, optical/RF MEMS, microfluidic chips, and other fields.

报告将阐述静电诱导自动图形化、静电透镜缩写、纳米多层膜器件层间键合、AI赋能等系列外场辅助先进制造技术原理与调控机制，深入剖析其在先进封装与具身智能等关键领域的应用实例，并对当前技术瓶颈、高密度异构集成封装挑战及未来智能化发展方向提出前瞻性展望，为外场辅助先进制造技术从实验室走向工程化应用提供理论支撑与路线指引。

This report will elucidate the principles and regulation mechanisms of a series of external-field-assisted advanced manufacturing technologies, including electrostatically induced automatic patterning, electrostatic lens, interlayer bonding of nano-multilayer-film devices, and AI-empowered techniques. It will conduct an in-depth analysis of their application cases in key domains such as advanced packaging and embodied intelligence, and present forward-looking perspectives on current technical bottlenecks, the challenges of high-density heterogeneous integration packaging, and future directions of intelligent development, thereby providing theoretical support and roadmap guidance for advancing external-field-assisted advanced manufacturing technologies from the laboratory to engineering applications.